Tech Briefs—Stitching Produces High Resolution CMOS Image Sensors

By: Kristin Lewotsky

By "stitching" lithographic exposures together, CMOS image sensor manufacturer Tower Semiconductor Ltd. has produced high-resolution detector arrays as large as a 6-in. silicon wafer. Widely used in other areas of semiconductor fabrication, stitching merges multiple design structures on a wafer during the photolithographic process, in this case creating a single CMOS image sensor (CIS) covering the entire wafer and avoiding the size limitation imposed by the exposure field of lithographic steppers. The accuracy of the process is such that the stitching lines are nearly undetectable (see Figure 1).

Increased array size
To achieve resolution equivalent to conventional 35-mm film-based cameras, image sensors for digital cameras integrate as many pixels as possible into a single chip. A typical stepper such as the Nikon model used at the Tower foundry only has a 20 x 20 mm² exposure field, however. Larger fields may be attainable at 1X exposures, but the minimum feature size is then only 1 µm, rather than the 0.5 µm features required for the sensor design.

Stitching technology overcomes the exposure-field limitation by merging multiple design structures on the wafer to create a single CIS. The stepper exposes one such design structure at a time. A high-precision alignment method allows these structures to slightly overlap, fusing them into a single integral chip. The wafer is manufactured, and the chip tested, sawed, and packaged as an integral unit. The stitched chip is for all practical purposes the same as a chip manufactured in the standard manner.

The Nikon stepper offers an alignment accuracy of approximately 0.1 µm, making the stitching process straightforward even in multiple-layer processes. The technique does impose certain design limitations on the width, spacing, and number of layers in the design along the borders, to ensure accurate connections. According to process engineer Aviram Matosevich, technique does not affect yield or increase the number of dead pixels. The defect density for sample sensors is 0.1 to 0.2 defects/cm².

Coupling structures
Although stitching technology has been used in the manufacture of charge-coupled device (CCD) detectors, it is less well-accepted in the CMOS domain. Large CIS arrays also will yield substantially better than CCD sensors, as unlike in CCD, the CIS pixels are not coupled electrically for the sensor operation. At IMEC, a European center for microelectronics research, engineers have used the stitching technology for a device designed in a 0.5-µm process that would otherwise not be producible. "Even when inspected using a microscope, it is virtually impossible to detect the stitching borders on the device," said senior design engineer Guy Meynants.