Improving BSI Architecture

While the performance breakthroughs associated with our new image sensor design mainly rest on its BSI architecture, there’s more to the design. The new sensor also has several design features that boost performance beyond what BSI could accomplish alone — particularly related to the ability to read out the massive amounts of imaging data at high speeds and improve throughput. 

Solving Analog-to-Digital Conversion Challenges

Embedding analog-to-digital converters (ADC) on CMOS image sensors is standard practice, but the BSI sensor’s speed required a massive increase in the amount of ADC. While modern CMOS image sensors typically have between 1,000 and 10,000 embedded ADC, the new BSI high-speed sensor has 40,000 ADC, each converting every 523 ns and generating a large amount of data to off-load from the sensor. To accomplish this task, it incorporates 160 high-speed serial outputs operating at greater than 5 Gbps. This technology is common on CPUs and FPGAs but new on a high-speed imaging sensor.