Datasheet: Model YVX-657 TDC 64-Channel Time-to-Digital Converter

The FPGA-based processor records the differential time of arrival between a reference time and pulse arriving on any of the 8 CMOS input channels or 64 LVDS channels, with <35 ps of timing jitter. For each channel, up to 65,535 32-bit time stamps can be recorded, at a maximum input event rate of up to 125 million events per second for each channel. The time stamps are stored in on-board memory before download to PC through gigabit Ethernet at a data rate of 100 MB/s.

The product was designed for easy integration with silicon photomultiplier (SiPM) and single-photon-sensitive Geiger-mode avalanche photodiode detectors. The product is available for immediate delivery to OEM system integrators.